cpp/openttd-patchpack/source Changeset - r25990:2674824c1e00

Changeset - r25990:2674824c1e00

Parent rev.

Child rev.

[Not reviewed]

master

0 1 0

r-a-sattarov - 3 years ago 2021-09-26 09:12:35
51679282+r-a-sattarov@users.noreply.github.com

Add: use of Intel Intrinsics & RDTSC on e2k (MCST Elbrus 2000) (#9575)

MCST e2k (Elbrus 2000) architecture has half native / half software support of most Intel/AMD SIMD
e.g. MMX/SSE/SSE2/SSE3/SSSE3/SSE4.1/SSE4.2/AES/AVX/AVX2 & 3DNow!/SSE4a/XOP/FMA4

E2K - this is VLIW/EPIC architecture, like Intel Itanium (IA-64) architecture.
Ref: https://en.wikipedia.org/wiki/Elbrus_2000

Co-authored-by: Alexander Troosh @troosh, Konstantin Ivlev @sse4 and Dmitry Shcherbakov @crypto-das

1 file changed with 30 insertions and 0 deletions:

src/cpu.cpp

0 comments (0 inline, 0 general)

src/cpu.cpp

➞

Show inline comments

@@ @@ -73,6 +73,18 @@ uint64 ottd_rdtsc() @@
 # define RDTSC_AVAILABLE
 #endif
 /* rdtsc for MCST Elbrus 2000 */
 #if defined(__e2k__) && !defined(RDTSC_AVAILABLE)
 uint64 ottd_rdtsc()
+{
 	uint64_t dst;
 # pragma asm_inline
 	asm("rrd %%clkr, %0" : "=r" (dst));
 	return dst;
+}
 # define RDTSC_AVAILABLE
 #endif
 #if defined(__EMSCRIPTEN__) && !defined(RDTSC_AVAILABLE)
 /* On emscripten doing TIC/TOC would be ill-advised */
 uint64 ottd_rdtsc() {return 0;}
@@ @@ -131,6 +143,24 @@ void ottd_cpuid(int info[4], int type) @@
 	);
 #endif /* i386 PIC */
+}
 #elif defined(__e2k__) /* MCST Elbrus 2000*/
 void ottd_cpuid(int info[4], int type)
+{
 	info[0] = info[1] = info[2] = info[3] = 0;
 	if (type == 0) {
 		info[0] = 1;
 	} else if (type == 1) {
 #if defined(__SSE4_1__)
 		info[2] |= (1<<19); /* HasCPUIDFlag(1, 2, 19) */
 #endif
 #if defined(__SSSE3__)
 		info[2] |= (1<<9); /* HasCPUIDFlag(1, 2, 9) */
 #endif
 #if defined(__SSE2__)
 		info[3] |= (1<<26); /* HasCPUIDFlag(1, 3, 26) */
 #endif
+	}
+}
 #else
 void ottd_cpuid(int info[4], int type)
+{

0 comments (0 inline, 0 general)